Summary: Cerebras unveiled the CS-4 rack-scale inference system and WSE-3T Turbo wafer on August 19, claiming up to 30 times faster inference than GPUs. The Turbo wafer reuses WSE-3 silicon and raises power delivery rather than introducing a new chip. Cerebras also shifts prompt prefill to AWS Trainium and AMD Instinct while keeping decode on its wafers.
Cerebras used August 19 to unveil the CS-4, its next-generation rack-scale inference system, along with a wafer it calls the WSE-3T “Turbo.” The headline pitch: a single rack serves inference up to 30x faster than GPUs, with a stated aim of multiplying the previous generation’s throughput per watt by ten. The Register and The Next Platform both ran detailed write-ups that same day, and the first CS-4 systems should come online before this quarter ends.
For a company whose reputation rests on proving that one wafer is the chip, the most telling decision here is a negative one: no new chip was built.
Same Silicon, Driven Harder
The T in WSE-3T does stand for Turbo, yet nothing underneath it is new silicon. The process node, the 46,225 square-millimeter wafer area, the transistor count, the core count, and the 44 GB of on-wafer SRAM all match the WSE-3 from two years ago. The change sits in power delivery: Cerebras says its new design drives twice the power through the wafer, which permits higher operating frequencies and faster token generation. The Register puts the clock near 2.8 GHz, up from 1.4 GHz before.
A doubling follows everywhere as a result. A single wafer now delivers 250 petaFLOPS of AI compute (a sparse figure), 43.2 PB/s of memory bandwidth, and 2.4 Tbps of off-die connectivity — twice the old 1.2 Tbps. Chip-to-chip latency drops from five microseconds to two, a change that matters as much as any bandwidth figure.
A Rack Built From Backpacks, Power Shelves, and a 2D Torus
One CS-4 takes as many as three WSE-3T wafers, packaged as “backpacks”: self-contained modules carrying all their control electronics on board, slid in from the rear of the rack, with the front given over to power shelves. Like NVIDIA’s NVL72 and AMD’s Helios, the CS-4 splits compute, power delivery, and cabling into modular pieces meant for datacenter deployment and maintenance. The Register estimates a full system at 120 to 140 kW. Monstrous as that sounds, it reads as almost conservative next to the 240 to 250 kW racks AMD and NVIDIA are expected to ship later this year.
The interconnect deserves equal attention. Switches are gone: chips talk to one another directly across a 2D torus, a grid whose edges wrap around to meet the opposite side. Cerebras claims the topology scales to models of up to 50 trillion parameters, a size no shipped model reaches today. A switched fabric remains available via RoCE over Ethernet, at somewhat higher latency. Low latency is exactly what permits the simplest form of multi-chip inference, pipeline parallelism: model weights spread across wafers, and work flowing through them one chip after another, with no tensor-parallel gymnastics required.
Inference Gets Split: Prefill Moves to Trainium and Instinct
The larger architectural move is Cerebras stepping back from running the entire inference stack on its own silicon. Prefill — the compute-hungry prompt-processing stage — now lands on AWS Trainium accelerators and AMD Instinct GPUs, leaving the Cerebras wafers the stage they handle best: decode, where the enormous on-wafer SRAM keeps weights and KV-caches next to the compute. Serving a trillion-parameter model once took thousands of accelerators; a few dozen wafers now suffice, with the exact count depending on the precision at which the weights are stored.
Impressive Figures, If You Read the Fine Print
The figure making the rounds comes from Artificial Analysis: on one CS-4 system, gpt-oss-120b serves up to 4,400 tokens per second per user, against roughly 350 tokens per second for the fastest GPU-based inference service available today. A gap that wide reshapes product decisions for latency-sensitive applications.
The Register attaches two sobering footnotes. First, 250 PFLOPS depends on sparsity; expressed as dense FP16 it lands nearer 25 PFLOPS — still impressive, far less spectacular than the slide implies. Second, the peak memory bandwidth is likely theoretical: the WSE-3 could never saturate its own SRAM during LLM inference, and nothing about the Turbo wafer suggests that changed.
Takeaways for Developers and Buyers
Three points stand out. First, the rack has become the unit of competition: NVIDIA’s NVL72, AMD’s Helios, and Cerebras’s CS-4 all define deployment by the rack, so procurement conversations shift from “how many cards” to “how many racks.” Second, heterogeneous inference is now mainstream — when even Cerebras concedes that prefill need not run on its wafers, there is little excuse for bolting every stage of a pipeline to one kind of accelerator. Third, with the first systems landing this quarter, teams choosing a backend for latency-critical voice or agentic workloads have a genuinely new option to benchmark, alongside the incumbents they already test.