Summary: Researchers at Zhejiang Lab and Fudan University introduced EaPU, a memristor training method reported on January 18, 2026 that cuts energy use nearly a million-fold versus GPUs. It reduces write operations by over 99% and extends device lifetime about 1,000x by replacing most small writes with probabilistic full-threshold pulses. Validation covered deep simulations and a 180nm physical array, but not LLM-scale training.
On January 18, 2026, TechXplore put the spotlight on a Nature Communications paper from a team at Zhejiang Lab and Fudan University. The method it introduces, EaPU (error-aware probabilistic update), lets memristor-based neural networks train on nearly six orders of magnitude — close to a million times — less energy than GPUs, while write operations drop by more than 99% and device lifetime stretches by roughly a thousand-fold.
For an industry weighed down by the power bill of compute, this work takes an uncommon angle: it goes after the problem at the very bottom of the hardware stack. The model is untouched, the training objective is untouched; what gets redesigned is the weight update — the most frequently executed hardware operation of all.
EaPU Builds the Algorithm Around Hardware Noise
At the root of the problem sits a basic incompatibility. Backpropagation rests on the assumption that weight updates are deterministic and can be nudged in tiny, exact steps. Memristors refuse to behave that way: an identical voltage pulse produces a different conductance change on every application, and device relaxation lets write errors pile up over time. The hardware noise contaminates the gradients outright, and training falls apart.
Rather than trying to beat the noise, EaPU works alongside it. Whenever the weight change a step calls for falls below a threshold value, the algorithm abandons the small write and does this instead: it fires a single full-threshold pulse with probability proportional to how large the intended change is — and if the probability does not land, the write is dropped entirely. Averaged out, the mean update remains unchanged, so training performance holds; in practice, writes turn rare. Under 0.1% of parameters require an update at each step, which on a 152-layer ResNet works out to 0.86 writes per thousand parameters.
Unpacking the Million-Fold Energy Gap
Read the figures as three stacked layers. EaPU trains on roughly 50 times less energy than previous memristor training approaches, roughly 13 times less than MADEM, the state of the art at the time, and sits nearly six orders of magnitude below GPU training. As the team points out, numerous studies had already confirmed how energy-efficient memristor-based in-memory computing is; what kept that efficiency out of reach was write errors accumulating over time under device relaxation.
Cutting writes also pays a second dividend: endurance. Write cycles set the ceiling on a memristor’s usable life, so trimming updates by more than two orders of magnitude buys roughly 1,000x longer device lifetime. For deployment the arithmetic is direct — a fixed batch of hardware completes more training rounds and serves longer. Anyone sizing clusters should note the knock-on effect too: less writing means less energy drawn by the write path itself and less heat to dissipate, savings that compound at rack scale in ways per-chip benchmarks understate.
Proof on Two Tracks: Deep Simulations and a Physical Array
Validation ran along two tracks. On simulations, ResNets reaching 152 layers and Vision Transformers went through testing; on noisy hardware, EaPU beat standard backpropagation with accuracy gains above 60%. On physical hardware, the team fabricated its own 180-nanometer memristor array and ran image denoising and super-resolution tasks, posting structural similarity scores of 0.896 and 0.933 respectively — level with or ahead of conventional training. Most memristor papers stop short of real analog arrays and quietly retreat to simulation, so having silicon-level numbers at all sets this work apart from the bulk of the literature.
The point that matters: the probabilistic scheme never traded accuracy for energy. Through its probabilistic transform, EaPU reshapes the magnitude distribution of updates while holding “the average value of the updates unchanged to guarantee training performance” — the design decision the whole method stands on.
The Distance to LLM Training
The gap to production deserves a straight answer. The physical validation so far has run on a compact 180nm array doing image restoration, not language modeling; the simulations do cover deep CNNs and ViTs, but memristor training at LLM scale remains an ambition on paper rather than a result. The team’s own next steps point two ways: carry EaPU over to other memory technologies such as ferroelectric transistors and magnetoresistive RAM, and explore training clusters for large language models. The code has been released publicly on Zenodo.
Infrastructure decision-makers can leave their purchase orders alone this quarter. What the study marks out instead is a scaling path unlike “stack more GPUs”: when the energy bottleneck of training lives in data movement and writes rather than computation itself, algorithm-hardware co-design is where the real leverage sits. Keep EaPU on the watchlist, and wait to see it replicate on larger models.