On March 11, 2026, Meta’s engineering team published “Four MTIA Chips in Two Years: Scaling AI Experiences for Billions,” laying out four generations of its in-house Meta Training and Inference Accelerator: the MTIA 300, 400, 450, and 500. The company says hundreds of thousands of MTIA chips are already deployed in production, with the remaining three generations rolling out through 2026 and 2027. CNBC reports that a single Meta data center rack will hold 72 MTIA 400 chips optimized for AI inference.
The timing is part of the story. The announcement landed only weeks after Meta’s expanded NVIDIA partnership, which covers millions of chips. Reuters notes that the last three chips arrive this year and in 2027, with the final two — the 450 and 500 — designed for inference. Meta is not choosing between vendors and silicon; it is running both as permanent product lines.
From Ranking Models to GenAI: Four Chips, Four Jobs
Each chip targets a different workload, and together they trace MTIA’s drift from ranking and recommendation into generative AI:
- MTIA 300 handles ranking and recommendation training and is already serving production traffic. Its design adds NIC chiplets, message engines, and near-memory compute.
- MTIA 400 extends the workload range from ranking into GenAI. It pairs two compute chiplets, and 72 chips form a rack-scale scale-up domain. Lab testing is complete and data center deployment is underway.
- MTIA 450 is tuned specifically for GenAI inference, with hardware acceleration for attention and FFN operations (Softmax, FlashAttention) and custom low-precision data types. Mass deployment is planned for early 2027.
- MTIA 500 stacks a 2x2 compute-chiplet layout alongside SoC and network chiplets to push inference efficiency further, arriving later in 2027.
The Spec Jumps: 25x Compute, 4.5x Bandwidth
The generational numbers Meta published are steep: from MTIA 300 to 500, HBM bandwidth rises 4.5x and compute FLOPS rise 25x. Generation by generation:
- 400 over 300: +400% FP8 FLOPS, +51% HBM bandwidth
- 450 over 400: 2x HBM bandwidth, +75% MX4 FLOPS — and 6x MX4 versus FP16/BF16 performance
- 500 over 450: +50% HBM bandwidth, up to +80% HBM capacity, +43% MX4 FLOPS
Low-precision formats are the through-line. When formats like MX4 are supported natively at the hardware and data-type level, per-token inference cost keeps falling — which is why Meta keeps swapping silicon for workloads that are already running. You do not redesign a chip family every six months for prestige; you do it because steady-state inference at Meta’s scale turns single-digit percentage efficiencies into real money.
How a Six-Month Cadence Works
Meta claims it can now ship a new chip roughly every six months. Traditional chip design cycles run two to three years, and compressing that is not magic — it is an architecture decision. The MTIA 400, 450, and 500 share one chassis, rack, and network platform, with compute delivered as reusable chiplets. A new generation changes the chiplet mix and the packaging, not the surrounding platform.
It is software-style modularity moved into silicon: freeze the interfaces, then swap the compute blocks like Lego bricks. For a company running ranking and recommendation for billions of users every day, platform stability and iteration speed stop being a trade-off.
Not Replacing Nvidia — Layering
Reading this as “Meta dumping Nvidia” gets the direction wrong. The expanded NVIDIA deal announced weeks earlier covers large-scale training and next-generation systems; MTIA absorbs the high-volume, cost-sensitive steady-state workloads — ranking, recommendations, and increasingly GenAI inference. It is layering, not replacement. The MTIA family is developed in close partnership with Broadcom, and CNBC frames the rollout as Meta’s cost play on its own workloads alongside the enormous GPU purchases.
The same week offered a telling contrast. Reports put Meta’s flagship Avocado model on hold until at least May (analysis here), yet the silicon roadmap is holding to its six-month beat. Model timelines slip; infrastructure commitments are stickier. Losing a round in the model race is recoverable — falling behind on inference cost structure bleeds margin every single day.
What It Means for Developers and Infrastructure Teams
- The in-house silicon playbook will spread. Meta has validated chiplet modularity as a way to compress iteration cycles; other hyperscale buyers will follow, and “a generation roughly every six months” may become the new baseline rather than an outlier.
- Quantization strategy now follows hardware. With MX4 and FP8 supported natively at the accelerator level, serving stacks need to re-examine precision choices and unit economics instead of defaulting to whatever ran last quarter.
- Multi-sourcing is the 2026 operating assumption. Meta simultaneously holds a huge NVIDIA order, Google TPU capacity, and its own MTIA line — compute acquisition is a separate battlefield from the model race, and application architectures should assume the accelerator underneath them keeps changing.
Sources
- Four MTIA Chips in Two Years: Scaling AI Experiences for Billions — Meta AI
- Meta rolls out in-house AI chips weeks after massive Nvidia order — CNBC
- Meta unveils plans for batch of in-house AI chips — Reuters
AI-assisted summary compiled from the sources above, reviewed by a human before publishing.