Summary: Meta’s March 11, 2026 engineering post unveiled MTIA 300, 400, 450, and 500, with hundreds of thousands of chips already in production and the final three arriving in 2026–2027. The roadmap shifts from ranking toward generative AI, with MTIA 400 and 500 optimized for inference and a shared chiplet platform enabling roughly six-month generations. The article says MTIA layers alongside NVIDIA purchases rather than replacing them.
Meta’s engineering blog carried a post titled “Four MTIA Chips in Two Years: Scaling AI Experiences for Billions” on March 11, 2026, unveiling four generations of the company’s homegrown Meta Training and Inference Accelerator: the MTIA 300, 400, 450, and 500. According to Meta, hundreds of thousands of these chips already run in production, while the three remaining generations arrive across 2026 and 2027. Per CNBC, a single Meta data center rack will house 72 MTIA 400 chips, which are optimized for AI inference.
When the news landed matters too. Barely weeks had passed since Meta widened its NVIDIA partnership, a deal covering millions of chips. Reuters points out that the final three chips arrive this year and in 2027, and that the last pair — the 450 and 500 — are built for inference. This is not an either-or between outside GPUs and in-house silicon: Meta runs both as standing product lines.
Four Chips, Four Workloads: Ranking to GenAI
Every chip in the lineup is aimed at its own workload, and read in sequence they map MTIA’s shift away from ranking and recommendation toward generative AI:
- MTIA 300 covers ranking and recommendation training and is already live in production. NIC chiplets, message engines, and near-memory compute are all part of its design.
- MTIA 400 broadens the coverage from ranking workloads into GenAI. Two compute chiplets sit inside it, and 72 chips together form a rack-scale scale-up domain. Lab testing has wrapped up, and data center deployment has started.
- MTIA 450 is built expressly for GenAI inference: attention and FFN operations (Softmax, FlashAttention) get hardware acceleration, and custom low-precision data types are supported. Volume deployment is scheduled for early 2027.
- MTIA 500 arranges compute as a 2x2 chiplet layout with SoC and network chiplets alongside it, to lift inference efficiency another notch; it arrives later in 2027.
Generation over Generation: 25x FLOPS, 4.5x Bandwidth
The cross-generation figures Meta published climb steeply: going from MTIA 300 to 500 means 4.5x the HBM bandwidth and 25x the compute FLOPS. Taken one step at a time:
- 400 versus 300: FP8 FLOPS up 400%, HBM bandwidth up 51%
- 450 versus 400: HBM bandwidth doubles, MX4 FLOPS up 75% — with MX4 delivering 6x the performance of FP16/BF16
- 500 versus 450: HBM bandwidth up another 50%, capacity up to 80% higher, MX4 FLOPS up 43%
The thread running through the roadmap is low precision. Once formats such as MX4 are native at both the hardware and the data-type level, the cost of inferring each token keeps dropping — and that explains why Meta keeps replacing silicon under workloads that are already live. Nobody rebuilds a chip family twice a year for show; at Meta’s scale, steady-state inference turns single-digit percentage efficiency gains into real money.
What Makes a Six-Month Cadence Possible
By Meta’s account, a fresh chip generation now ships about every six months. Chip design has traditionally taken two to three years, and squeezing that down comes from an architectural decision rather than magic: the MTIA 400, 450, and 500 sit on a shared chassis, rack, and network platform, while compute is delivered as reusable chiplets. What a new generation changes is the chiplet mix and the packaging — the surrounding platform stays untouched.
Think of it as the software world’s modularity transplanted into silicon: interfaces get locked down first, after which compute units can be swapped like building blocks. Platform stability and iteration speed therefore stop being mutually exclusive.
Layering, Not a Nvidia Exit
To read this as “Meta walking away from Nvidia” is to get the direction backwards. The widened NVIDIA deal announced just weeks earlier spans large-scale training and next-generation systems; MTIA takes on steady-state workloads where volume is high and cost sensitivity is acute — ranking, recommendations, and increasingly GenAI inference. The two stack in layers; neither replaces the other. Broadcom collaborated closely on the entire MTIA family, and CNBC describes the rollout as Meta’s cost play on its own workloads in addition to the enormous GPU purchases.
That same week supplied a pointed contrast. Reporting has Meta’s flagship Avocado model delayed until at least May (analysis here), yet the silicon roadmap holds its six-month beat without slipping. Model schedules wobble; infrastructure commitments hold firm. Dropping a round in the model race can be won back — losing ground on inference cost structure drains margin every single day.
Takeaways for Developers and Infrastructure Teams
- The in-house silicon playbook will travel. Meta has proven that chiplet modularity compresses iteration cycles; other buyers at hyperscale will copy it, and a generation roughly every six months could shift from outlier to new normal.
- Quantization strategy now trails the hardware. With MX4 and FP8 native at the accelerator level, serving stacks have to rework precision choices and cost models rather than coasting on whatever ran last quarter.
- Multi-sourcing is the working assumption for 2026. A huge NVIDIA order, Google TPU capacity, and the in-house MTIA line all sit in Meta’s portfolio at once — acquiring compute is its own battlefield, separate from the model race, and application architectures should assume the accelerator underneath keeps changing.