On March 11, 2026, Synopsys used its new flagship conference, Converge 2026 in Santa Clara, to launch a broad set of design, verification, and simulation tools aimed squarely at the exploding complexity of AI chips. Reuters framed the news simply as new software for designing AI chips; the venue itself — a rebranded, two-day event on March 11 and 12 — matched the ambition. It is also the first time the company has folded technology from its $35 billion Ansys acquisition into the main product line, which makes this launch as much an integration milestone as a product one.
CEO Sassine Ghazi’s keynote pitched a “silicon to systems” design paradigm — silicon-powered, AI-enabled, and software-defined. His one-liner: “The complexity of next-generation intelligent systems requires a completely new engineering approach.” AMD, Intel, Microsoft, and NVIDIA all appeared in the customer lineup.
Silicon to Systems: A Repositioning Launch
The structure of the announcement signals a repositioning: Synopsys is selling an end-to-end flow from transistor to system, not isolated point tools. The same week, at Embedded World, the company announced an Electronics Digital Twins (eDT) platform, automotive-first, that lets OEMs complete up to 90% of software validation before any hardware exists — a meaningful shift for programs where silicon availability gates everything downstream. Converge also brought a Synopsys-AMD-Microsoft collaboration to speed access to Synopsys EDA tools on Microsoft platforms using AMD compute, a small but telling datapoint in the running battle over who supplies the machines that run chip design.
AgentEngineer: Multi-Agent Workflows Enter Chip Verification
The headline item is AgentEngineer, what Synopsys calls an industry-first L4 orchestrated multi-agent workflow for design and verification. It generates RTL from natural language and formal specs, runs Lint checks, builds unit-level testbenches, and iterates-verifies until targets converge. The numbers do the arguing: front-end verification of a large SoC normally takes teams four to six months, and the workflow has delivered 2x productivity gains — up to 5x in some cases. It is built on standard SDKs and APIs rather than a closed stack, with collaborations involving AMD, Microsoft (Foundry and Discovery), and NVIDIA. That plumbing detail matters: teams are more likely to adopt an agent layer they can script, audit, and partially roll out than a black-box flow that owns the whole pipeline.
Multiphysics Fusion: First Fruits of the Ansys Deal
Multiphysics Fusion technology blends Synopsys and Ansys tooling to attack voltage drop, thermal, and electromagnetic coupling effects in advanced-node chips. Initial applications cover timing signoff, multi-die design, design closure, and analog/mixed-signal. It is in beta with early-access customers now, with production expected “in the coming months.” Alongside it, Ansys 2026 R1 — the first major Ansys release since the acquisition — adds agentic and generative AI simulation (the Mesh Agent in Mechanical, GeomAI for geometry concepts, and the Discovery Validation Agent) plus three cross-company integrations: VC FSM with medini analyze for functional safety, QuantumATK with Granta MI for materials data, and OptoCompiler with Lumerical FDTD for photonics, including automated Verilog-A model generation.
AI-Infused Simulation and Hardware Verification
Hardware-assisted verification got software-defined updates too: up to 2x performance on ZeBu Server 5 and 2x capacity scaling. The new HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms target mainstream designs with doubled capacity, and an industry-first test automation feature catches cache-coherency and subsystem bugs earlier in the cycle, where they are cheapest to fix.
What It Means for Chip Design Teams
Three practical effects. First, verification is where schedules and budgets go to die — if a four-to-six-month front-end effort reliably compresses by half, product planning math changes outright. The spread between 2x and 5x depends on how much of the flow you hand over, so early-customer data is worth tracking before betting a tapeout on it. Second, integration speed is the real test of this launch: Multiphysics Fusion is still beta, and the gap between “coming months” and shipped product decides whether the $35 billion Ansys bet pays off. Third, orchestrated multi-agent workflows have officially entered hardware design — “AI designs the AI chips” is now a roadmap item rather than a slogan. For engineering teams, that shifts weight toward spec-writing and agent orchestration skills, and tool-chain selection should start scoring this kind of automation as a first-class criterion.
Sources
- Synopsys rolls out new software tools for designing AI chips — Reuters
- Synopsys Outlines Vision for Engineering the Future — Synopsys
- Synopsys Unveils New AI Chip Design Tools After Major Acquisition — Times of AI
AI-assisted summary compiled from the sources above, reviewed by a human before publishing.