Summary: South Korean chip startup XCENA said on May 29, 2026 that it had closed a $135 million Series B at a $570 million valuation, lifting its total funding to $185 million. For developers watching inference bills climb, this is a path worth keeping an eye on. Launched in 2022 by three founders who all came out of Samsung and SK Hynix, the company is taking the opposite side of the AI buildout’s standard story: what truly constrains inference is not GPU compute — it is memory.
South Korean chip startup XCENA said on May 29, 2026 that it had closed a $135 million Series B at a $570 million valuation, lifting its total funding to $185 million. Launched in 2022 by three founders who all came out of Samsung and SK Hynix, the company is taking the opposite side of the AI buildout’s standard story: what truly constrains inference is not GPU compute — it is memory.
That wager aims at the priciest lines on any LLM serving invoice: the spillover that begins once KV caches outgrow onboard GPU memory, and the latency created by carting data back and forth among CPUs, GPUs, and DRAM. For developers watching inference bills climb, this is a path worth keeping an eye on.
Why the Bottleneck Sits in Memory
Once an LLM’s KV cache no longer fits within a GPU’s onboard memory, it has to spill into slower external DRAM, and latency climbs at once. On top of that, most models flush the cache after every user query, so each turn piles on redundant computation of its own. CEO Jin Kim is direct about it: “CPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that.” As he frames it, inference “isn’t just a compute problem; it’s increasingly a memory scaling problem.” The market backdrop lines up as well: in May, Samsung, SK Hynix, and Micron each crossed a trillion-dollar valuation for the first time, with memory suppliers now sitting at the heart of AI demand.
MX1: Bringing Compute to the Doorstep of DRAM
The MX1 has not left the prototype stage. Its organizing idea is to lean on CXL (Compute Express Link) and station compute next to DRAM, so preprocessing, KV cache management, and data caching all get carried out inside the memory module rather than having data run relays across CPUs, GPUs, and memory. On the hardware side, thousands of deliberately small RISC-V cores are combined with in-house designs for the memory hierarchy, the interconnect bus, and the DRAM controller. SiliconANGLE supplies further architectural specifics: up to 2TB of DRAM per device; cores grouped four to a cluster, each carrying its own L1 cache, with those clusters arranged into larger ones around shared memory pools; KV cache reuse spanning requests; and gains for analytics workloads of the Apache Spark variety. On the company’s telling, a workload that used to need ten servers now fits on one. Software-wise, XCENA offers porting APIs, lower-level optimization APIs, and a simulation tool for reliability testing, all intended to cut integration friction.
The $135M Series B and the Countdown to Production
Atinum Investment and IMM Investment, both of Seoul, co-led the round; Corstone Asia joined as well, while SBI Investment and Mirae Asset Capital — already investors — committed again. The company also notes that talks with international investors over additional capital are underway. Proceeds will fund new computational memory products, a faster go-to-market push, and closer collaboration with hyperscalers. The schedule leaves little slack: the MX1 will be built on Samsung’s 4-nanometer process, with mass production targeted for the end of 2026 and revenue to follow in 2027. More than 90 people work at the company, spread across Pangyo, South Korea, and Sunnyvale, California. All three founders — CEO Jin Kim, CTO Dohun Kim, and CPO Harry Juhyun Kim — have Samsung and SK Hynix roots, which counts for a lot when the product is a memory controller that hyperscalers must trust.
Rivals in View: Astera Labs and Marvell
The head-to-head competitors are two Nasdaq-listed companies: Astera Labs and Marvell. Kim separates the camps on architecture: going by public specs, Marvell’s comparable offerings rely on “a handful of general-purpose cores,” while XCENA developed its own many-core IP — “We have thousands of cores.” The customer set is plainly drawn too: hyperscalers that spend tens of billions of dollars a year on AI infrastructure, along with global memory vendors still in early-stage conversations.
Possible Effects on Inference Costs
Three observations. First, the memory wall has moved into the top tier of inference economics; once the CXL ecosystem matures, the cost structure of long-context and agent workloads gets rewritten. Second, should cross-request KV cache reuse hold up in practice, it strips away redundant prefill — an immediate saving for services running at high concurrency. Third, the timeline risk deserves respect: compressing the jump from prototype to mass production into a single year, with revenue expected in 2027, leaves almost no margin for error, and any stumble hands an opening to competitors equipped with far deeper pockets. Developers need not re-architect anything today, though “memory bandwidth per dollar” merits a spot in every model-selection and serving-cost spreadsheet.