Summary: At CES on January 5, 2026, AMD framed its roadmap around a shift toward yotta-scale AI compute. The company announced Helios, rated at up to 3 AI exaflops per rack, along with the MI440X for on-premises enterprise AI and Ryzen AI 400 mobile processors with 60-TOPS NPUs. The launch also emphasized ROCm as a common stack from cloud systems to client devices.
January 5, 2026, Las Vegas: AMD Chair and CEO Dr. Lisa Su opened the company’s CES set under the banner “AI Everywhere, for Everyone,” with Michael Kratsios, director of the White House Office of Science and Technology Policy, sharing the stage. The framing skipped the pleasantries. Global compute capacity, AMD argues, will swell from roughly 100 zettaflops today past 10 yottaflops inside five years. “We are entering the era of yotta-scale computing,” Su declared, “and AMD is building the compute foundation for this next phase of AI.”
Where NVIDIA’s CES 2026 keynote built its story around physical AI, AMD spread its narrative across the full stack: rack-scale training infrastructure, on-premises enterprise systems, and the NPU living inside a laptop. For developers and buyers, the organizing principle outweighs any single announcement — AMD now plots its roadmap explicitly against a yotta-scale demand curve.
Helios: 3 AI Exaflops in a Single Rack
The data center headliner goes by “Helios,” a rack-scale platform rated by AMD at up to 3 AI exaflops per rack. Its building blocks: Instinct MI455X GPUs, EPYC “Venice” CPUs, and Pensando “Vulcano” NICs, laced together by the ROCm software stack. AMD brands Helios “the blueprint for yotta-scale infrastructure” and aims it squarely at trillion-parameter training.
Beside Helios came the Instinct MI440X, a fresh GPU pointed at on-premises enterprise AI — training, fine-tuning, and inference packed into a compact eight-GPU form factor. The earlier-announced MI430X, for its part, drives the AI factory supercomputers, Discovery at Oak Ridge National Laboratory among them, along with Alice Recoque, France’s first exascale system.
Further down the roadmap waits the MI500 series, previewed for 2027: CDNA 6 architecture, a 2nm process, and HBM4E memory. AMD’s engineers project AI performance of up to 1,000x the MI300X — a rack-versus-platform comparison and a pre-release estimate that may shift, but the signal reads clean: AMD means to meet NVIDIA’s current generation at every point in time, not chase the previous one.
The Client Side: Ryzen AI 400 and a 60-TOPS NPU
On the client front, AMD rolled out the Ryzen AI 400 and Ryzen AI PRO 400 series, whose NPUs carry 60 TOPS — comfortably over the Copilot+ PC bar. First systems ship in January 2026, with wider OEM availability through Q1. Outlets such as Tom’s Hardware and TechPowerUp cover these mobile chips under the “Gorgon Point” codename — in essence a raised-clocks, stronger-NPU refresh of Strix Point — while the PRO commercial line follows later in 2026 behind the 12-core Ryzen AI 9 HX 475.
The more developer-relevant entries are the Ryzen AI Max+ 392 and Max+ 388: with 128GB of unified memory, AMD claims they can run models of up to 128 billion parameters on the local machine. A companion Ryzen AI Halo developer platform — a small-form-factor desktop — arrives in Q2, and the Ryzen AI Embedded P100/X100 series chases edge workloads from automotive cockpits to humanoid robotics. The pitch that recurs through it all: ROCm now stretches from cloud to client, so one software investment pays out at both ends.
OpenAI and the Ecosystem Partners
The partner list strung through the keynote and the release spans models, robotics, and biotech: OpenAI, Luma AI, Liquid AI, World Labs, Blue Origin, AstraZeneca, Absci, and Illumina. The list’s assignment is to show the Instinct ecosystem is no supercomputer-only tale — video generation, world models, and protein design workloads are all settling onto AMD silicon.
Two side signals merit a note as well: AMD pledged $150 million toward expanding AI education in classrooms and communities, tied to a White House initiative, and more than 15,000 students joined the AMD AI Robotics Hackathon run with Hack Club.
What It Means for Developers and Buyers
Three practical takeaways. First, the MI440X knocks another notch out of the barrier to self-hosted inference — where data sovereignty or unit economics veto the cloud, an eight-GPU rack appliance earns a slot on the 2026 shortlist. Second, the pairing of a 60-TOPS NPU with 128GB of unified memory converts “run a big model locally” from trade-floor demo into a plannable product feature; teams should already be scheduling model distillation and NPU inference pipelines. Third, AMD’s full-stack story — one ROCm from cloud to edge — keeps closing the distance to the CUDA ecosystem. A multi-vendor strategy has outgrown procurement insurance; it is now an option with a genuine engineering path underneath.