AI Infrastructure

AMD at CES 2026: Helios Racks and the Yotta-Scale AI Play

At CES 2026 Lisa Su laid out AMD's AI Everywhere vision: Helios racks at up to 3 AI exaflops each, new MI455X and MI440X GPUs, a 2027 MI500 preview, and 60-TOPS Ryzen AI 400 chips.

AMD at CES 2026: Helios Racks and the Yotta-Scale AI Play — article cover

On January 5, 2026, AMD Chair and CEO Dr. Lisa Su took the CES stage in Las Vegas under the banner “AI Everywhere, for Everyone,” joined by Michael Kratsios, director of the White House Office of Science and Technology Policy. The framing was blunt. Global compute capacity, AMD argues, will grow from roughly 100 zettaflops today to more than 10 yottaflops within five years. “We are entering the era of yotta-scale computing,” Su said, “and AMD is building the compute foundation for this next phase of AI.”

Where NVIDIA’s CES 2026 keynote centred on physical AI, AMD spread its story across the whole stack: rack-scale training infrastructure, on-premises enterprise systems, and the NPU inside a laptop. For developers and buyers, the single product announcements matter less than the organizing principle — AMD is now planning its roadmap explicitly against a yotta-scale demand curve.

Helios: 3 AI Exaflops in a Single Rack

The data center headline is “Helios,” a rack-scale platform AMD says delivers up to 3 AI exaflops per rack. The building blocks: Instinct MI455X GPUs, EPYC “Venice” CPUs, and Pensando “Vulcano” NICs, all tied together by the ROCm software stack. AMD calls Helios “the blueprint for yotta-scale infrastructure” and points it straight at trillion-parameter training.

Alongside Helios, AMD announced the Instinct MI440X, a new GPU aimed at on-premises enterprise AI — training, fine-tuning, and inference in a compact eight-GPU form factor. The previously announced MI430X, meanwhile, powers AI factory supercomputers including Discovery at Oak Ridge National Laboratory and Alice Recoque, France’s first exascale system.

The longer-range roadmap item is the MI500 series, previewed for 2027: CDNA 6 architecture, a 2nm process, and HBM4E memory. AMD’s engineers project up to a 1,000x AI performance gain over the MI300X — a rack-versus-platform comparison and a pre-release projection that may well change, but the signal is clear. AMD intends to match NVIDIA’s next generation at each point in time, not chase its previous one.

The Client Side: Ryzen AI 400 and a 60-TOPS NPU

On the client side, AMD introduced the Ryzen AI 400 and Ryzen AI PRO 400 series with NPUs rated at 60 TOPS, clearing the Copilot+ PC bar. First systems ship in January 2026, with broader OEM availability in Q1. Outlets like Tom’s Hardware and TechPowerUp report these mobile chips under the “Gorgon Point” codename — effectively a raised-clocks, stronger-NPU refresh of Strix Point — with the PRO commercial line led by the 12-core Ryzen AI 9 HX 475 arriving later in 2026.

More interesting for developers are the Ryzen AI Max+ 392 and Max+ 388: with 128GB of unified memory, AMD claims they can run models of up to 128 billion parameters locally. A matching Ryzen AI Halo developer platform — a small-form-factor desktop — lands in Q2, and the Ryzen AI Embedded P100/X100 series targets edge workloads from automotive cockpits to humanoid robotics. The recurring pitch is that ROCm now spans cloud to client, so the same software invests in both.

OpenAI and the Ecosystem Partners

The partner list in the keynote and release spans models, robotics, and biotech: OpenAI, Luma AI, Liquid AI, World Labs, Blue Origin, AstraZeneca, Absci, and Illumina. For AMD, that list’s job is to prove the Instinct ecosystem is not just a supercomputer story — video generation, world models, and protein design workloads are all landing on AMD silicon.

Two side signals are worth noting too: AMD pledged $150 million to expand AI education in classrooms and communities, tied to a White House initiative, and more than 15,000 students joined the AMD AI Robotics Hackathon run with Hack Club.

What It Means for Developers and Buyers

Three practical takeaways. First, the MI440X lowers the barrier for self-hosted inference another notch — if data sovereignty or unit economics rule out the cloud, an eight-GPU rack appliance belongs on the 2026 shortlist. Second, the combination of a 60-TOPS NPU and 128GB of unified memory turns “run a big model locally” from a demo into a plannable product feature; teams should be scheduling model distillation and NPU inference pipelines now. Third, AMD’s full-stack narrative — one ROCm from cloud to edge — is steadily closing the gap with the CUDA ecosystem. Multi-vendor strategy is no longer just procurement insurance; it is an option with a real engineering path behind it.

Sources

AI-assisted summary compiled from the sources above, reviewed by a human before publishing.

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